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interruption mask register [1 record]

Filter results by subject field Alphabetical list of terms

Filter results by subject field

Alphabetical list of terms

Record 1 1984-09-20

English

Subject field(s)
  • Computer Memories
DEF

In System/7, a 4 bit hardware register with one bit corresponding to each of the 4 priority interrupt levels; each bit setting specifies whether or not interrupts are recognized on that level.

French

Domaine(s)
  • Mémoires (Informatique)

Spanish

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