TERMIUM Plus^®

Fiche 1,  Justifications,  Anglais

Record number: 1, Textual support number: 1 CONT

In a military context, the term "Through Life Support, "among other definitions, is used to describe an arrangement between a service provider and a branch of the armed forces, where the responsibility, and risk, of operating an aircraft is delegated to the original system supplier or designated support partner. This trend sees defence moving away from acquiring a military system, the acquisition of a military capability. With the acquisition of the hardware comes a guarantee that the supplied product will meet a list of specific criteria, including, for example, pre-determined levels of dispatch reliability and availability.  3, fiche 1, Anglais, - through%2Dlife%20support

Fiche 1,  Justifications,  Français

Record number: 1, Textual support number: 1 CONT

Alors que toute augmentation significative du budget d'équipement britannique paraît exclue dans le moyen terme, les activités de BAE [BAE Systems plc] vont se résumer de plus en plus à des «partenariats» avec le MoD [Ministry of Defence] en tant que fournisseur de services de soutien sur la durée de vie (through-life support) tel que défini par la «Defense Industrial Strategy (DIS)» publiée fin 2005.  1, fiche 1, Français, - service%20de%20soutien%20sur%20la%20dur%C3%A9e%20de%20vie

Fiche 1,  Justifications,  Espagnol

Fiche 2,  Justifications,  Anglais

Record number: 2, Textual support number: 1 DEF

Interrupting the activity in progress and switching to another activity. Context switching occurs as one process after another is scheduled for execution. The operating system saves the interrupted process’ hardware context in its hardware process control block(PCB) using the Save Process Context instruction, loads another process’ hardware PCB into the hardware context using the Load Process Context instruction, scheduling that process for execution.  4, fiche 2, Anglais, - context%20switching

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Fiche 2,  Justifications,  Espagnol

Fiche 3,  Justifications,  Anglais

Record number: 3, Textual support number: 1 DEF

A data structure used to contain process context. The hardware PCB contains the hardware context. The software PCB contains the software context, which includes a pointer to the hardware PCB.  1, fiche 3, Anglais, - process%20control%20block

Fiche 3,  Justifications,  Français

Record number: 3, Textual support number: 1 DEF

Bloc de commande automatique d'opérations industrielles en continu.  1, fiche 3, Français, - bloc%20de%20commande%20de%20processus

Fiche 3,  Justifications,  Espagnol

Fiche 4,  Justifications,  Anglais

Record number: 4, Textual support number: 1 DEF

A data structure known to the processor that contains the hardware context when a process is not executing. A process's hardware PCB resides in its process header.  1, fiche 4, Anglais, - hardware%20process%20control%20block

Record number: 4, Textual support number: 1 OBS

Terminology of Digital Equipment Corporation.  2, fiche 4, Anglais, - hardware%20process%20control%20block

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Fiche 5,  Justifications,  Anglais

Record number: 5, Textual support number: 1 DEF

The values contained in the following registers while a process is executing: the program counter (PC); the Processor Status Longword (PSL); the 14 general registers (R0 through R13); the four processor registers (P0BR, P0LR, P1BR and p1LR) that describe the process virtual address space; the Stack Pointer (SP) for the current access mode in which the processor is executing; plus the contents to be loaded in the stack pointer for every access mode other than the current access mode.  1, fiche 5, Anglais, - hardware%20context

Record number: 5, Textual support number: 1 OBS

Terminology of Digital Equipment Corporation.  2, fiche 5, Anglais, - hardware%20context

Fiche 5,  Justifications,  Français

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Fiche 6,  Justifications,  Anglais

Record number: 6, Textual support number: 1 DEF

The stack pointer for the interrupt stack. Unlike the stack pointers for process context stacks, which are stored in the hardware PCB, the interrupt stack pointer is stored in an internal register.  1, fiche 6, Anglais, - interrupt%20stack%20pointer

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Fiche 6,  Justifications,  Espagnol