TERMIUM Plus^®

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There is only one page table for system space, the system page table(SPT), that translates all system space references. SPT is described by its two hardware registers, the system base register(SBR) and the system length register(SLR).  2, fiche 1, Anglais, - system%20base%20register

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Record number: 2, Textual support number: 1 CONT

Hardware description : an unambiguous method of describing the interconnection and behavior of the electrical and electronic subset of the computer hardware. There are a number of computer hardware description languages(CHDLs) that work at the register transfer level; the most well known are AHPL(a hardware programming language) and CDL(computer description language).  1, fiche 2, Anglais, - computer%20hardware%20description%20language

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Registres internes [...] : ce sont des registres contenus dans le microprocesseur. Ils permettent de mémoriser des données échantillonnées sur le bus de données BD et de réaliser rapidement des opérations autonomes entre accumulateur et registre ou entre registre et registre.  1, fiche 3, Français, - registre%20interne

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The process register, or its equivalent in a hardware process control block, that contains the base virtual address of the page table entry for virtual page number 0 in a process program region.  1, fiche 4, Anglais, - program%20region%20base%20register

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The processor register, or its equivalent in a hardware process control block, that contains the number of entries in the page table for a process program region.  1, fiche 5, Anglais, - program%20region%20length%20register

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We present a new way of organizing virtual memory management hardware using real-address-based hardware page address registers.  1, fiche 6, Anglais, - real%2Daddress%2Dbased%20hardware%20page%20address%20register

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Fiche 7,  Justifications,  Anglais

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On the MUG-G, the virtual store was implemented using the same philosophy as the Atlas scheme, that is, there was a page address register for every page in the main store hence full coverage of the store. Hardware PARs removed the need for page tables in the store since all the pages in the store are recovered by the PARs  1, fiche 7, Anglais, - hardware%20PAR

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Fiche 8,  Justifications,  Anglais

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The stack pointer for the interrupt stack. Unlike the stack pointers for process context stacks, which are stored in the hardware PCB, the interrupt stack pointer is stored in an internal register.  1, fiche 8, Anglais, - interrupt%20stack%20pointer

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In System/7, a 4 bit hardware register with one bit corresponding to each of the 4 priority interrupt levels; each bit setting specifies whether or not interrupts are recognized on that level.  1, fiche 9, Anglais, - interruption%20mask%20register

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