TERMIUM Plus^®

Record 1,  Textual support,  English

Record number: 1, Textual support number: 1 CONT

Gate camouflaging is a technique for obfuscating the function of a circuit against reverse engineering attacks. However, if an adversary has pre-existing knowledge about the set of functions that are viable for an application, random camouflaging of gates will not obfuscate the function well.  1, record 1, English, - gate%20camouflaging

Record 1,  Textual support,  French

Record number: 1, Textual support number: 1 CONT

Le camouflage de portes logiques consiste à utiliser une bibliothèque de portes particulièrement conçues pour ne pas permettre l'identification simple par une analyse microscopique de la puce lors de la rétro-ingénierie.  1, record 1, French, - camouflage%20de%20portes%20logiques

Record 1,  Textual support,  Spanish

Record number: 1, Textual support number: 1 OBS

Técnica de ofuscación para impedir la falsificación de circuitos integrados.  1, record 1, Spanish, - camuflaje%20de%20puertas%20l%C3%B3gicas

Record 2,  Textual support,  English

Record number: 2, Textual support number: 1 DEF

[A] device which performs a fixed unitary operation on selected qubits in a fixed period of time.  4, record 2, English, - quantum%20logic%20gate

Record number: 2, Textual support number: 1 CONT

In quantum computing and specifically the quantum circuit model of computation, a quantum logic gate(or simply quantum gate) is a basic quantum circuit operating on a small number of qubits. They are the building blocks of quantum circuits, like classical logic gates are for conventional digital circuits.  5, record 2, English, - quantum%20logic%20gate

Record 2,  Textual support,  French

Record number: 2, Textual support number: 1 DEF

Dispositif qui transforme l'état quantique d'un ou de plusieurs qubits physiques pour permettre l'exécution d'un algorithme quantique.  3, record 2, French, - porte%20logique%20quantique

Record number: 2, Textual support number: 1 CONT

En informatique quantique, et plus précisément dans le modèle de circuit quantique de calcul, une porte quantique (ou porte logique quantique) est un circuit quantique élémentaire opérant sur un petit nombre de qubits. Les portes quantiques sont les briques de base des circuits quantiques, comme le sont les portes logiques classiques pour des circuits numériques classiques.  4, record 2, French, - porte%20logique%20quantique

Record number: 2, Textual support number: 1 OBS

Une porte quantique à plusieurs qubits entraîne en général leur intrication quantique.  3, record 2, French, - porte%20logique%20quantique

Record number: 2, Textual support number: 2 OBS

porte quantique : désignation, définition et observation publiées au Journal officiel de la République française le 20 décembre 2022.  5, record 2, French, - porte%20logique%20quantique

Record 2,  Textual support,  Spanish

Record number: 2, Textual support number: 1 CONT

Puertas cuánticas. Los ordenadores clásicos están compuestos por puertas lógicas como AND, OR y NOT. Estas puertas están conectadas por cables que van de la salida de una a la entrada de otra. En cambio, los ordenadores cuánticos están compuestos por puertas cuánticas, que realizan cambios en las probabilidades de obtener un estado base. Además, las puertas cuánticas son reversibles, a diferencia de la mayoría de las puertas lógicas clásicas.  2, record 2, Spanish, - puerta%20l%C3%B3gica%20cu%C3%A1ntica

Record 3,  Textual support,  English

Record number: 3, Textual support number: 1 CONT

ASIC [application-specific integrated circuit] synthesis tools do not report area in terms of gate count. If you want to represent area in terms of equivalent gate count, then divide the design's cell area by the area of the smallest NAND [not and] cell available in the library.  2, record 3, English, - equivalent%20gate%20count

Record 3,  Textual support,  French

Record 3,  Textual support,  Spanish

Record 4,  Textual support,  English

Record number: 4, Textual support number: 1 CONT

Basic gate propagation delay time... means the propagation delay time value corresponding to the basic gate used in a "monolithic integrated circuit".  2, record 4, English, - basic%20gate%20propagation%20delay%20time

Record 4,  Textual support,  French

Record 4,  Textual support,  Spanish

Record 5,  Textual support,  English

Record number: 5, Textual support number: 1 CONT

Every expression of boolean algebra corresponds to a logic circuit. The letters used in the expression are represented by the inputs to the circuit. Each wire in the circuit represents some part of the expression. A gate takes the values from its input wires and combines them with the appropriate word--and, or, or not--to produce the label on its output wire.  2, record 5, English, - output%20line

Record 5,  Textual support,  French

Record 5,  Textual support,  Spanish

Record 6,  Textual support,  English

Record number: 6, Textual support number: 1 OBS

gate firing circuit : term officially approved by the Lexicon Project Committee(New Brunswick).  2, record 6, English, - gate%20firing%20circuit

Record 6,  Textual support,  French

Record number: 6, Textual support number: 1 OBS

circuit d'amorçage de la gâchette : terme uniformisé par le Comité du projet de lexiques (Nouveau-Brunswick).  2, record 6, French, - circuit%20d%27amor%C3%A7age%20de%20la%20g%C3%A2chette

Record 6,  Textual support,  Spanish

Record 7,  Textual support,  English

Record number: 7, Textual support number: 1 DEF

A logic component that can be assembled together with other IP blocks and custom circuitry to implement a given system in ASIC [application-specific integrated circuit] or FPGA [field-programmable gate array] technology.  3, record 7, English, - intellectual%20property%20block

Record number: 7, Textual support number: 1 CONT

IP blocks are a fundamental concept for the electronic design automation (EDA) industry, as they represent the basic unit for reuse.  3, record 7, English, - intellectual%20property%20block

Record 7,  Textual support,  French

Record number: 7, Textual support number: 1 DEF

Ensemble électronique dont l'utilisation pour la conception de circuits intégrés est protégée par les règles de la propriété intellectuelle.  1, record 7, French, - bloc%20de%20propri%C3%A9t%C3%A9%20intellectuelle

Record number: 7, Textual support number: 1 OBS

Un bloc de propriété intellectuelle peut notamment être décrit sous une forme logique, à l'aide d'un schéma électrique ou de manière topologique.  1, record 7, French, - bloc%20de%20propri%C3%A9t%C3%A9%20intellectuelle

Record number: 7, Textual support number: 2 OBS

bloc de propriété intellectuelle; BPI; bloc de PI : termes, abréviation et définition publiés au Journal officiel de la République française le 1er avril 2015.  3, record 7, French, - bloc%20de%20propri%C3%A9t%C3%A9%20intellectuelle

Record 7,  Textual support,  Spanish

Record 8,  Textual support,  English

Record number: 8, Textual support number: 1 DEF

Gate circuit whose output is energized only when certain signals are present, in order to prevent other signals from occurring at the inputs.  2, record 8, English, - inhibit%20gate

Record 8,  Textual support,  French

Record number: 8, Textual support number: 1 DEF

Porte logique employée pour interdire un autre signal.  1, record 8, French, - circuit%20A%20MOINS%20QUE

Record 8,  Textual support,  Spanish

Record number: 8, Textual support number: 1 DEF

Circuito usado como un conmutador y situado por lo general en paralelo con el circuito en su controlador.  1, record 8, Spanish, - puerta%20de%20inhibici%C3%B3n

Record 9,  Textual support,  English

Record number: 9, Textual support number: 1 CONT

Gate Array. A type of ASIC [Application-Specific Integrated Circuit] in which the transistors, gates, and other active circuit elements are fixed on a wafer called a "master slice".  2, record 9, English, - master%20slice

Record 9,  Textual support,  French

Record number: 9, Textual support number: 1 DEF

Rondelle de silicium sur laquelle les transistors et résistances sont déja diffusés.  2, record 9, French, - circuit%20mosa%C3%AFque

Record number: 9, Textual support number: 1 OBS

Il ne reste plus qu'à les interconnecter entre eux à la demande pour la rondelle en fonction de la logique désirée.  2, record 9, French, - circuit%20mosa%C3%AFque

Record number: 9, Textual support number: 1 CONT

Circuit mosaïque [...]. On part d'une mosaïque de composants disposés régulièrement sur la surface du circuit; les niveaux de diffusion sont communs à plusieurs circuits [...], mais les niveaux de métallisation permettent une personnalisation du circuit par une interconnexion entre composants spécifiques des fonctions à réaliser [...]  2, record 9, French, - circuit%20mosa%C3%AFque

Record 9,  Textual support,  Spanish

Record 10,  Textual support,  English

Record number: 10, Textual support number: 1 CONT

VHDL is the VHSIC(Very High Speed Integrated Circuit) Hardware Description Language. VHDL is an international standard specification language for describing digital hardware used by industry worldwide. VHDL enables hardware modeling from the gate to system level. VHDL provides a mechanism for digital design and reusable design documentation.  2, record 10, English, - very%20high%20speed%20integrated%20circuit%20hardware%20description%20language

Record 10,  Textual support,  French

Record 10,  Textual support,  Spanish

Record 11,  Textual support,  English

Record number: 11, Textual support number: 1 DEF

A circuit wherein the drain terminal of a transistor is placed at signal ground. The input signal is applied between gate and source terminals. The output signal is obtained from across the source resistor. This circuit is also known as the source follower circuit because the output phase of the signal follows that of the input signal.  1, record 11, English, - common%2Ddrain%20circuit

Record 11,  Textual support,  French

Record 11,  Textual support,  Spanish

Record 12,  Textual support,  English

Record number: 12, Textual support number: 1 DEF

A circuit wherein the gate terminal of an FET is placed at signal ground. The input signal is applied between the source and gate terminals and the output obtained from the drain section. There is no phase reversal between input and output signals. Another term for this system is the grounded gate circuit.  1, record 12, English, - common%2Dgate%20circuit

Record 12,  Textual support,  French

Record 12,  Textual support,  Spanish

Record 13,  Textual support,  English

Record number: 13, Textual support number: 1 DEF

An integrated logic circuit including a programmable input gate array of AND gates and a non-programmable output array of OR gates.  1, record 13, English, - programmable%20array%20logic%20circuit

Record number: 13, Textual support number: 1 OBS

Programmable array logic of the capabilities of field programmable logic arrays but are simpler to be programmed by a PROM programmer.  1, record 13, English, - programmable%20array%20logic%20circuit

Record 13,  Textual support,  French

Record number: 13, Textual support number: 1 DEF

Circuit logique intégré comportant une matrice prédiffusée programmable de portes ET en entré et une matrice prédiffusée non programmable de portes OU en sortie.  1, record 13, French, - circuit%20PAL

Record number: 13, Textual support number: 1 OBS

Les circuits PAL possèdent une grande partie des possibilités des réseaux logiques programmables par l'utilisateur tout en étant plus simples à programmer grâce à l'emploi d'un programmateur de mémoires mortes programmables.  1, record 13, French, - circuit%20PAL

Record 13,  Textual support,  Spanish

Record 14,  Textual support,  English

Record number: 14, Textual support number: 1 DEF

The time that it takes a gate circuit to shut off a current.  1, record 14, English, - turn%2Doff%20time

Record 14,  Textual support,  French

Record number: 14, Textual support number: 1 OBS

De l'impulsion.  1, record 14, French, - temps%20de%20coupure

Record 14,  Textual support,  Spanish

Record 15,  Textual support,  English

Record number: 15, Textual support number: 1 CONT

logical circuit elements have two output states, namely one or zero, and in modern high-gain circuits one of these outputs is achieved even if the input is not in either of these conditions. Thus, a loose connection or poor input gate will still cause the output of the following gate to be either one or zero. A failure in the logical network occurs when one or more outputs or inputs are always zero or always one under all network conditions. Thus, n logical element that fails is said to be either stuck at zero(s-a-0) or stuck at one(s-a-1).  1, record 15, English, - stuck%20at%20one

Record 15,  Textual support,  French

Record number: 15, Textual support number: 1 OBS

Voir bloqué sur une boucle.  2, record 15, French, - bloqu%C3%A9%20%C3%A0%20un

Record 15,  Textual support,  Spanish

Record 16,  Textual support,  English

Record number: 16, Textual support number: 1 CONT

Logical circuit elements have two output states, namely one or zero, and in modern high-gain circuits one of these outputs is achieved even if the input is not in either of these conditions. Thus, a loose connection or poor input gate will still cause the output of the following gate to be either one or zero. A failure in a logical network occurs when one or more outputs or inputs are always zero or always one under all network conditions. Thus, a logical element that fails is said to be either stuck at zero(s-a-0) or stuck at one(s-a-1).  1, record 16, English, - stuck%20at%20zero

Record 16,  Textual support,  French

Record number: 16, Textual support number: 1 OBS

Voir bloqué sur une boucle.  2, record 16, French, - bloqu%C3%A9%20%C3%A0%20z%C3%A9ro

Record 16,  Textual support,  Spanish

Record 17,  Textual support,  English

Record number: 17, Textual support number: 1 DEF

Switched semiconductor which, unlike the classic thyristor, requires no external turn-off circuit to switch off current, but can be blocked by a controlled electrode, or gate.  1, record 17, English, - GTO%20thyristor

Record 17,  Textual support,  French

Record number: 17, Textual support number: 1 DEF

Semi-conducteur commandable qui, à la différence des thyristors classiques, ne nécessite pas de circuit d'extinction extérieur pour interrompre la circulation du courant, mais peut être bloqué au moyen de l'électrode de commande (gâchette).  1, record 17, French, - thyristor%20GTO

Record number: 17, Textual support number: 1 OBS

Technique de l'ingénieur, 9, 1973, Lexique E 1075, p. 7, Glossaire 58.  2, record 17, French, - thyristor%20GTO

Record 17,  Textual support,  Spanish

Record 18,  Textual support,  English

Record number: 18, Textual support number: 1 CONT

A gate valve supervisory switch. [Sprinkler system supervisory device] The switch is attached to the two sides of the valve yoke by the hook bolts.... When the valve is wide open, the tip of the plunger enters a 1/8-in. deep depression drilled in the valve stem. The switch is adjusted so that in the open valve position the contact ring closes the electric circuit between the contact blades.  1, record 18, English, - gate%20valve%20supervisory%20switch

Record 18,  Textual support,  French

Record 18,  Textual support,  Spanish

Record 19,  Textual support,  English

Record number: 19, Textual support number: 1 DEF

Function of setting up a topological discrete model representing the structure of a logic gate network; used to evaluate a circuit during initial design stage and to determine fault test sequences.  2, record 19, English, - logic%20simulation

Record 19,  Textual support,  French

Record 19,  Textual support,  Spanish

Record 20,  Textual support,  English

Record number: 20, Textual support number: 1 OBS

gate circuit : A circuit that passes a signal only when a gating pulse is present.  2, record 20, English, - multiple%20pulse%20gate%20circuit

Record 20,  Textual support,  French

Record number: 20, Textual support number: 1 OBS

gating circuit : circuit de contrôle.  2, record 20, French, - circuit%20de%20contr%C3%B4le%20%C3%A0%20impulsions%20multiples

Record 20,  Textual support,  Spanish

Record 21,  Textual support,  English

Record number: 21, Textual support number: 1 OBS

In the practical circuit(...), the positive gate drive current is fed from the positive DC rail via the emitter-follower transistor T1 and the parallel connection of the zener diode D2 and capacitor C1 to the gate of the GTO switch.  1, record 21, English, - emitter%2Dfollower%20transistor

Record 21,  Textual support,  French

Record number: 21, Textual support number: 1 OBS

Dans le circuit simple (...), un courant positif s'écoule de l'alimentation continue dans la grille du GTO [gate-turn off switch], par l'intermédiaire du transistor T1 monté en émetteur suiveur de la diode zener D2 et d'une capacité C1 montée en parallèle.  1, record 21, French, - transistor%20en%20%C3%A9metteur%20suiveur

Record 21,  Textual support,  Spanish